The ever-increasing computational demand, the advent of artificial intelligence (AI), and the bottleneck of the traditional CMOS-based Von Neumann architecture has raised a debate concerning energy sustainability. To circumvent these challenges, it is paramount to seek for alternative hardware implementations. Examples of energy efficient unconventional computing solutions are brain-inspired systems including 3rd generation spiking neural networks (SNNs). Traditionally, the prevailing computing paradigm has involved the transmission of continuous floating variables from one processing unit to another. However, insights from neurobiology and brain-inspired computing underscore that SNN communicate through discrete pulses. As a fundamental building block component for such hardware implementations, emerging non-volatile memories (eNVMs) stand out as promising memory component, which outperform and exceeds complementary metal-oxide-semiconductor (CMOS) based technologies in processing and non-volatile storage capabilities. Yet, it inherently suggests the colocation of memory and processing units in in-memory computing hardware solutions. To implement it in hardware, different solutions of eNVMs are investigated and benchmarked throughout the thesis. In chapter 3, As a case study, we analyze the memory solutions fabricated in the laboratories associated with this project. These solutions serve as a practical example to assess the efficacy and performance of different analog eNVM technologies. The solutions are Phase change memories provided by STMicroelectronics, TiO2 oxide based resistive memories from 3it and spin transfer torque magnetic memories from SPINTEC. Experimental characterization is conducted on PCM and TiO2 OxRAM, while data regarding SOT-MRAM is sourced from simulations or provided by the SPINTEC IC design team. The methodology employed to perform the electrical characterization and analog programming are depicted. The PCM, OxRAM and SOT-MRAM give rises to 44, 10, and 5 multilevel states respectively. Non-idealities aspects such as variability are also included in the analysis. The operation requirements are considered to further co-integrate these eNVMs into a 28 nm FD-SOI based neuron solution designed, tested, and depicted in chapter 4. A co-design methodology to co-integrate and implement in hardware eNVMs with FD-SOI based fully analog neurons is provided and a multi-project work (MPW) comprising an analog neuron, a current attenuator, and selectors for memory integration is deployed. According to test the analog neuron consumed 3.86 pJ/spike. Finally, the multilevel and drift behaviour of 1T1R PCM are exhaustively explored at cryogenic environments in chapter 5. The 1T1R PCMs are fully characterized at 300 K, 77 K and 12 K. The ePCM multilevel capabilities give rise to 10 multilevel states at 77 K, 12 K and 300 K. The performance and effect of non-idealities at different temperatures are modelled and evaluated in SNN MNIST classification task. The SNN classification accuracy is sustained up to 2 years at 77 K and 12 K while a 12% drop in accuracy is observed at 300 K. More importantly, without requiring any additional hardware or software solution for drift mitigation. In addition, a hardware and operation solution based on non-linear current scaling are proposed to mitigate the non-ideality aspects of 1T1R PCMs at room temperature, the coefficient of variability and the drift is reduced leading to a sustain and improvement of accuracy in a SNN MNIST classification task. The variability is reduced by up to 5% and the drift is compensated for years.

Plus d'information :https://www.spintec.fr/phd-defense-study-of-multilevel-emerging-non-volatile-memories-for-in-memory-computing-and-fd-soi-based-analog-snns/
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