In this talk, I will discuss why energy-efficient acceleration of cognitive-computing tasks in the era of big-data requires simultaneous consideration of multiple levels of the computing stack such as novel information encoding schemes, algorithm-to-architecture mapping, and integration of emerging resistive-switching technologies with CMOS such as magnetic tunnel junctions and memristors. I will illustrate this with three examples of non-Boolean encoding schemes that have been recently researched by my colleagues and I. This includes experimental demonstrations of analog encoding schemes with crossbar arrays of magnetic tunnel junctions for neural network acceleration; probabilistic encoding schemes with a pair of coupled superparamagnetic tunnel junctions for acceleration of combinatorial optimization; and temporal encoding schemes with crossbar arrays of multi-level resistive switches for graph computations.

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