L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technologyWith the maturity of CMOS
technologies and their use for low power various analog and digital
applications, some additional effects must be modeled or enhanced to improve the
accuracy of SPICE models. Indeed, with the decrease of supply voltages/currents
and the use of the back bias in Fully-Depleted Silicon On Insulator (FDSOI)
technologies, the devices operate close to the weak-moderate inversion, where
gm/Id figure is impacted by effects like the depletion of source/drain
electrodes and the parasitic currents such as Impact ionization current in
moderate inver-sion and Gate Leakage current in weak inversion, can have a
significant impact on the model accuracy. This paper describes the latest
significant improvements of L-UTSOI model (formerly Leti-UTSOI) related to
version 102.4. These model extensions are validated against Silicon experimental
data.